1. Field of the Invention
The invention relates in general to integrated circuits, and more particularly, to minimization of crosstalk effects in circuits.
2. Description of the Related Art
Signal integrity refers to the degree to which a signal within an integrated circuit faithfully propagates to its intended destinations within its allocated timeframe. Static timing analysis (STA) is one approach to analyze signal integrity. More recently, statistical static timing analysis (SSTA) has been used to analyze signal integrity in circuits designs in which fabrication process variations have a greater impact upon signal integrity.
STA involves computing the expected timing of a digital circuit to verify that all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured. STA typically aims to find worst-case delay of a circuit over all possible input combinations. Integrated circuit manufacturing processes are inherently imperfect. In some circumstances, traditional STA techniques cannot adequately model the variability inherent in semiconductor manufacturing processes.
For example, at extremely small dimensions such as 45 nm, semiconductor manufacturing process control is difficult, and even slight variations in the duration, temperature and chemical concentrations can result in physical differences in devices and interconnects from one wafer to the next and from one die to the next leading to variations in their electrical behavior. Even if the amount of process variation remains the same in absolute terms as in previous designs with larger dimensions, that variation accounts for a greater percentage change in overall device performance at the smaller design dimensions. In the past, STA based signal integrity techniques often compensated for such process variability through aggressive insertion of guard bands or by using multiple corners involving different timing scenarios to reflect different manufacturing conditions. Unfortunately, such a corner-based approach can be overly pessimistic since it can involve timing scenarios that have an extremely small likelihood of occurring.
Fabrication process based variations in integrated circuits has resulted in increasing reliance upon SSTA techniques that treat delays as probability density functions (PDFs) that take into account the statistical distribution of parametric variations when analyzing a circuit. The basic SSTA method defines random variations of delay as random variables and calculates a probability density function (PDF) of circuit delay. SSTA expresses pin-to-pin delays and arrival times as PDFs; whereas STA typically expresses such values as single numbers.
SSTA solutions typically use a sensitivity-based approach to model the effect of variation on timing. This ordinarily involves establishing how change in a particular device or interconnect parameter, such as oxide or wire thickness, affects a desired property, such as slew or capacitance. This “sensitivity” to the parameter in conjunction with its probability distribution (e.g., mean and standard deviation) provides a statistical model describing the probability that a parameter will have a certain effect on a device or interconnect property. Device parameters may include oxide thickness, gate length and width, voltage threshold, and interconnect parameters can include metal width, thickness, spacing and dielectric properties. A subset of these parameters may be selected which have a significant impact on timing and used for characterization. Careful selection of parameters is important in order to keep the runtime for SSTA manageable while maintaining accuracy.
It is possible to then use this parameter variation information for timing analysis by generating models that define sensitivities to these parameters. For a circuit, these sensitivities, are typically are generated during library characterization, represent how a change in a particular parameter affects circuit performance such as delay, slew, setup, or hold time. For interconnect, these sensitivities represent how a change in each parameter affects resistance, capacitance, and inductance, and are generated during extraction. The sensitivities for circuit elements (e.g., gates) and interconnects along with the distribution information for each parameter can be used to generate PDFs for arrival time (data path), required time (clock path), and slack which include the overall effect of all the parameters on timing. A PDF, therefore, can represent variability of circuit characteristics such as signal arrival time, required time, and slack caused by variability of multiple fabrication processes.
FIG. 1 is an illustrative chart of signal arrival time showing hypothetical best case and worst case arrival times for a signal computed using STA and showing a hypothetical PDF of arrival time of the signal determined based upon SSTA. In this example, the worst corner case arrival time is 2.3 ns according to STA. However, the 3-sigma yield point of the PDF, which provides a 99.9% confidence level, has a nominal arrival time of 1.9 ns. The shaded region indicates the reduction in worst case error margin that can be achieved in this illustrative example through sue of SSTA instead of STA. Thus, in this hypothetical example, SSTA allows a designer to shave off 400 ps from the cycle time, a path performance gain of 18.2%. The use of SSTA, therefore, can result in less pessimistic signal arrival time estimates, which can lead to in improved circuit design.
Crosstalk effects on signal integrity is becoming an increasingly important factor in circuit design. Recent advances in process technology scales the aspect ratio of wires to be taller and thinner to control wire resistance. A side effect of this scaling is that coupling capacitance between wires becomes the dominant portion of the total wire capacitance. In addition, signal transition times have become faster resulting in stronger aggressors on adjacent victim wires. Moreover, increasingly tighter timing margins require more accurate timing analysis and less overestimation of delay.
FIG. 2 is an illustrative drawing of a victim net 204 and an aggressor net 202 and a curve 206 representing aggressor-dependent delay change of arrival time of a victim net signal transition. It will be appreciated that an integrated circuit design ordinarily includes a multitude of gates and nets disposed nearby to each other so as to result in victim-aggressor relationships of the type described herein. STA in the presence of crosstalk typically involves finding a worst-case (i.e., corner case) delay among possible alignments of an aggressor net signal 208 with a victim net signal 210. The victim net 204 includes a victim net driver circuit 212 and a victim net receiver circuit 214. The aggressor net 202 includes an aggressor net driver circuit 216 and an aggressor net receiver circuit 218. Capacitive coupling 220 exists between the victim net and the aggressor net. The victim net driver circuit 212 produces a victim signal 210 that propagates to the victim net receiver circuit 214. The aggressor net driver circuit 216 produces an aggressor signal 208 that propagates to the aggressor net receiver circuit 218. Capacitance 220 between the victim and aggressor nets, 204 and 202, respectively, results in crosstalk between the two nets. The delay change curve 206 represents aggressor switching induced change in delay of a victim signal state transition. More particularly, crosstalk can result in delay changes of signal transitions on both nets. Note that although reference herein is made to ‘delay’ change, it will be appreciated that depending upon relative aggressor-victim switching directions and aggressor-victim switching time alignments, the victim and/or aggressor-transition may be delayed or speeded up. The family of curves within dashed lines 222 will be used to explain the relationship between aggressor switching and delay change in victim net signal transition from one state to another. The amount of the delay change is a function of not only the value of the cross capacitance 220, but also the relative switching time between the aggressor net 202 and the victim net 204.
Crosstalk delay change is a difference between crosstalk delay and nominal delay. Crosstalk delay change is the extra delay (or speed-up) in a victim net state transition (e.g., switching from logic 0 to 1 or from logic 1 to 0) induced by transitioning of some or all aggressors of the victim net. In general, for crosstalk delay analysis, the maximum of crosstalk delay change (taken absolute value) is of greatest interest. The delay change is positive when victim and aggressors switch in opposite directions and it is used for late arrival time calculation (often referred to as max delay analysis). Similarly, the delay change is negative when victim and aggressors switch in opposite directions and it is used for early arrival time calculation (often referred to as min delay analysis). Nominal delay is a stage delay when aggressors are held quiet (e.g., logical 0 or 1).
FIG. 3 is an enlarged drawing of a family of curves 222 shown in FIG. 2, that conceptually represent the impact of crosstalk upon victim signal transition arrival time. A first curve 302 shown with dashed lines represents a victim net signal transition for a victim net signal transmitted from the victim net driver 212 to the victim net receiver 214. An arrow 304 represents imparting of victim net delay change to the first curve 302 due to crosstalk between the victim net switching transition signal and an aggressor signal having a given alignment with the victim net signal. It will be appreciated that although only a single aggressor net is shown, multiple aggressors may in fact contribute to crosstalk effect upon a victim net. A second curve 306 represents a victim net signal transition as transformed due to crosstalk. A comparison of the first and second curves 302, 306 shows conceptually that the shape of the victim net signal transition has changed due to crosstalk, which corresponds to a change in the effective arrival time of the victim net signal transition at a victim net receiver gate 214.
In STA, there typically will be a range of time, in which a signal transition can possibly happen in a net. This range is usually termed as the switching window of the net. One goal of STA in the presences of crosstalk is to find the worst/best delay change on the net within the corresponding switching window constraints. As explained above, as integrated circuit technology scales down to nanometer dimensions, process variation has become an ever more important factor in signal timing estimation. STA has difficulty modeling such process variation.
Accordingly there is a need to use SSTA during signal integrity analysis to evaluate crosstalk induced delay change in very small dimension circuit designs. The present invention meets this need.